BUILT-IN SELF TEST FOR DETECTING STUCK-AT-FAULTS IN CMOS COMBINATIONAL LOGIC ICS

Widianto, Widianto and Syafaah, Lailis and Nurhadi, Nurhadi (2018) BUILT-IN SELF TEST FOR DETECTING STUCK-AT-FAULTS IN CMOS COMBINATIONAL LOGIC ICS. In: Seminar Nasional Teknologi dan Rekayasa (SENTRA). Universitas Muhammadiyah Malang, Malang, pp. 61-64. ISBN ISSN (Cetak) 2527-6042 eISSN (Online) 2527-6050

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Abstract

Stuck-at-faults may occur at input and output gates inside CMOS combinational logic ICs. The faults may be caused by an imperfect manufacturing process. Moreover, they may generate a function of the ICs becomes errors. There are two types of the faults, namely stuck-at-1 and stuck-at-0. The stuck-at-1 and the stuck-at-0 may affect logic values of the gates become 1 and 0, respectively. Thus, they should be detected early. In this paper, a built-in self test circuit is proposed to detect them. The test circuit consists of a linear feedback shift register and multiplexers. The shift register is made by D-flip flops and an XOR gate and is used to generate test vectors. The multiplexers are used as test selectors to select the ICs either in a normal mode or a test mode. Analysis results show that the stuck-at-faults at the combinational logic IC of xx855 can be detected by the test circuit.

Item Type: Book Section / Proceedings
Keywords: Stuck-At-Faults, Combinational Logic ICs, Built-In Self Test Circuit, Linear Feedback Shift Register, Multiplexers
Subjects: T Technology > TK Electrical engineering. Electronics Nuclear engineering
Divisions: Faculty of Engineering > Department of Electrical Engineering (20201)
Depositing User: faruq Amrul Faruq
Date Deposited: 06 Sep 2024 06:16
Last Modified: 06 Sep 2024 06:16
URI: https://eprints.umm.ac.id/id/eprint/10883

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