Widianto, Widianto and Hasani, M. Chasrun (2023) CAKUPAN VERIFIKASI TESTBENCH DALAM MENDETEKSI KERUSAKAN HUBUNG SINGKAT DI RANGKAIAN TERPADU KOMPARATOR. JITET (Jurnal Informatika dan Teknik Elektro Terapan), 11 (3 S1). pp. 1130-1138. ISSN 2830-7062
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Abstract
In this paper, a testbench is proposed to detect stuck-at-faults in a
comparator IC (Integrated Circuit). Moreover, the testbench utilized by a
functional coverage in each input and output of the IC. The testbench
composed by some components, i.e., transaction object, generator, interface,
driver, monitor, scoreboard, environment, test, and testbench top. The IC is
as a DUT (Design Under Test). Furthermore, the testbench and the DUT are
designed by a SystemVerilog language and verified by a Questasim 2021.1
simulator. Verification results show the stuck-at-faults occurring in the DUT
may be detected. The detected faults are indicated by error statements.
Further, the coverage of the faults is 94.44%
| Item Type: | Article |
|---|---|
| Keywords: | testbench; functional coverage; stuck-at-faults; comparator IC. |
| Subjects: | T Technology > TK Electrical engineering. Electronics Nuclear engineering |
| Divisions: | Directorate of Vocational Education > Diploma of Electronics Technology (20401) |
| Depositing User: | widianto Widianto, ST, MT |
| Date Deposited: | 26 Oct 2023 05:02 |
| Last Modified: | 26 Oct 2023 05:02 |
| URI: | https://eprints.umm.ac.id/id/eprint/351 |
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