A SIGNATURE REGISTER OF A BIST TO DETECT STUCK-AT-FAULTS IN COMBINATIONAL LOGIC ICS

Widianto, Widianto and Lis, Robert (2020) A SIGNATURE REGISTER OF A BIST TO DETECT STUCK-AT-FAULTS IN COMBINATIONAL LOGIC ICS. In: Prosiding Seminar Nasional Teknologi dan Rekayasa (SENTRA). Fakultas Teknik (FT), Universitas Muhammadiyah Malang(UMM), pp. 39-43. ISBN 2527-6042

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Abstract

A specific functionality of combinational logic ICs (integrated circuits) may become errors caused by occurring stuck-at-faults
at its inputs and output logic gates. The faults may be detected by a signature register of a BIST (built-in self test). A circuit
simulation of it is designed by Verilog. Moreover, as a CUT (circuit under test) is a combinational IC of XXX855 manufactured
by Nexperia Semiconductor Company. A testability of the circuit is simulated using QuestaSim simulator. Simulation results
show that the circuit may detect the faults occurring in the CUT

Item Type: Book Section / Proceedings
Keywords: stuck-at-faults, signature analyzer, BIST, combinational logic ICs
Subjects: T Technology > TK Electrical engineering. Electronics Nuclear engineering
Divisions: Directorate of Vocational Education > Diploma of Electronics Technology (20401)
Depositing User: widianto Widianto, ST, MT
Date Deposited: 26 Oct 2023 05:01
Last Modified: 26 Oct 2023 05:01
URI: https://eprints.umm.ac.id/id/eprint/354

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