Build Testbenches for Verification in Shift Register ICs using SystemVerilog

Widianto, Widianto and Hasani, M. Chasrun and Lis, Robert (2022) Build Testbenches for Verification in Shift Register ICs using SystemVerilog. International Journal of Electronics and Telecommunications, 68 (3). pp. 619-623. ISSN 2081-8491

[thumbnail of Widianto Chasrun Lis - verification shift register IC stuck-at-faults SystemVerilog.pdf]
Preview
Text
Widianto Chasrun Lis - verification shift register IC stuck-at-faults SystemVerilog.pdf

Download (524kB) | Preview
[thumbnail of Similarity - Widianto Chasrun Lis - verification shift register IC stuck-at-faults SystemVerilog.pdf]
Preview
Text
Similarity - Widianto Chasrun Lis - verification shift register IC stuck-at-faults SystemVerilog.pdf

Download (1MB) | Preview
Item Type: Article
Subjects: T Technology > TK Electrical engineering. Electronics Nuclear engineering
Divisions: Directorate of Vocational Education > Diploma of Electronics Technology (20401)
Depositing User: widianto Widianto, ST, MT
Date Deposited: 25 Oct 2023 04:52
Last Modified: 25 Oct 2023 04:52
URI: https://eprints.umm.ac.id/id/eprint/335

Actions (login required)

View Item
View Item