Widianto, Widianto and Lis, Robert (2022) Delay Analysis in HCMOS Logic ICs. In: AIP Conference Proceeding: 1ST INTERNATIONAL CONFERENCE ON TECHNOLOGY, INFORMATICS, AND ENGINEERING. Engineering, 2453 . AIP Publishing, 020059-1-020059-5.
Widianto Lis - HCMOS logic ICs Delays SPICE.pdf
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Abstract
Open defects may occur at interconnection between gates inside HCMOS logic ICs due to open metal at
imperfect fabrication process affecting speed responses of the ICs. A SPICE simulation is thus proposed to analyze delays
due to the defects inside the ICs. The ICs are designed from a HCMOS netlist library distributed by Nexperia Co. Ltd.
Simulation results indicate that the delays linearly increase along with sizes and locations of the defects.
| Item Type: | Book Section / Proceedings |
|---|---|
| Keywords: | Delay Analysis in HCMOS Logic ICs |
| Subjects: | T Technology > TK Electrical engineering. Electronics Nuclear engineering |
| Divisions: | Directorate of Vocational Education > Diploma of Electronics Technology (20401) |
| Depositing User: | widianto Widianto, ST, MT |
| Date Deposited: | 26 Oct 2023 04:55 |
| Last Modified: | 26 Oct 2023 04:55 |
| URI: | https://eprints.umm.ac.id/id/eprint/362 |
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